VHDL Code Generator

ALU

This page allows you to interactively design an arithmetic & logic unit. The schematic module diagram below will adjust to reflect the settings as you choose them. When you have selected your chosen options, press the "Generate VHDL" button and the tool will produce VHDL code corresponding to the configured ALU. You are free to cut and paste this code into your own projects.

Schematic Diagram
Diagram should appear here if you have enabled Java.

Design Specification

Design your ALU by specifying the following parameters…

Operands

The ALU has two source operands, a & b. These correspond with internal a & b buses. You may select the source inputs to be registered (useful when multiplexing a and b on a common bus.)

Source "a" width: bit(s) Latched in register "A": Sign extend: Zero extend: when shorter than "b".

Source "b" width: bit(s) Latched in register "B": Sign extend: Zero extend: when shorter than "a".

Shifter

The ALU can optionally incorporate a shift/rotate block in one of the input paths. A full multi-bit barrel shifter is an expensive resource in terms of gates/logic blocks, so the one implemented here is limited to single bit left and right logical and arithmetic (sign preserving) shifts and rotates. The shifter does not affect/incorporate the carry flag.

Implement shifter block: Shifter in operand path "a": Path "b":

Operations

Add the desired operations, specifying the op. code and arithmetic or logical operation required. The ALU allows functions on one or two operands (a & b) and optionally a carry (borrow) in for arithmetic operations.

Action	Op Code	Binary	Hex	ALU Operation	Shifter Operation

Delete selected

Add op. code(s)

Sort by op. code

Output

The output of the ALU can be tristated with a bus enable signal (useful if output and input buses are common or multiplexed) and/or registered.

Flags

Check the following boxes to implement the corresponding ALU output flag(s).

Carry out (C): Zero (Z): Sign negative (N): Overflow (V):

VHDL Source Code

The VHDL for your ALU will appear here when you press the Generate VHDL button…

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